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22–6
Table 22–9 shows the Dual-Clock FIFO block I/O formats.
Chapter 22: Storage Library
Table 22–9. Dual-Clock FIFO Block I/O Formats
(1)
,
I/O
Simulink
(2) (3)
VHDL
Type
(4)
I1 [L1].[R1]
I1: in STD_LOGIC_VECTOR({L1 + R1 - 1} DOWNTO 0)
Explicit
I
O
I2 [1]
I3 [1]
O1 [L1].[R1]
O2 [1]
O3 [1]
O4 [1]
O5 [1]
O6 [L2].[0]
O7 [L2].[0]
I2: in STD_LOGIC
I3: in STD_LOGIC
O1: out STD_LOGIC_VECTOR({L1 + R1 - 1} DOWNTO 0)
O2: out STD_LOGIC
O3: out STD_LOGIC
O4: out STD_LOGIC
O5: out STD_LOGIC
O6: out STD_LOGIC_VECTOR({L2 - 1} DOWNTO 0)
O7: out STD_LOGIC_VECTOR({L2 - 1} DOWNTO 0)
Explicit
Explicit
Explicit
Explicit
Explicit
Explicit
Explicit
Explicit-optional
Explicit-optional
Notes to Table 22–9 :
(1) For signed integers and signed binary fractional numbers, the MSB is the sign bit.
(2) [L] is the number of bits on the left side of the binary point; [R] is the number of bits on the right side of the binary point. For signed or unsigned
integers R = 0, that is, [L].[0]. For single bits, R = 0, that is, [1] is a single bit.
(3) I1 [L].[R] is an input port. O1 [L].[R] is an output port.
(4) Explicit means that the port bit width information is a block parameter. Implicit means that the port bit width information is set by the datapath
bit width propagation mechanism. To specify the bus format of an implicit input port, use a Bus Conversion block to set the width.
Figure 22–3 shows an example with the Dual-Clock FIFO block.
Figure 22–3. Dual-Clock FIFO Block Example
Dual-Port RAM
The Dual-Port RAM block maps data to an embedded RAM (embedded array block,
EAB; or embedded system block, ESB) in Altera devices. The read and write ports are
separate.
The Dual-Port RAM block accepts any data type as input. The input port always
registers and the output port can optionally be registered.
DSP Builder Handbook
Volume 2: DSP Builder Standard Blockset
November 2013 Altera Corporation
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